1. Field of the Invention
The present invention relates to a semiconductor wafer probing method.
2. Description of the Related Art
When many chips are formed on a semiconductor wafer in a semiconductor fabricating process, electric characteristics of these chips should be verified on the semiconductor wafer so as to screen defective chips. This verification is performed by a probe apparatus. The chips on the semiconductor wafer are verified by the probe apparatus in the following manner. Probe needles of the probe apparatus are contacted to electrode pads of chips on the semiconductor wafer. Predetermined voltages are applied to the electrode pads through the probe needles so as to perform electric tests such as chip connection test. The basic electric characteristics of each chip are tested by a tester.
In the conventional probe apparatus, as shown in FIGS. 17A and 17B, edge portions of a plurality of probe needles 31 are secured at a periphery of a center opening portion of a probe card (not shown) by a synthetic resin or the like. In other words, the edge portions are formed in an overhang shape. Thus, when eight chips T are verified by inclined probe needles shown in FIG. 17A at the same time, a probe card having two rows of overhand probe needles that face each other is used. In addition, two rows of electrode pads of chips T are disposed in such a manner that two electrode pads are arranged in vertical direction and four electrode pads are arranged in horizontal direction. This electrode pad arrangement is defined as one index region. Thereafter, all the chips T on the semiconductor wafer are divided into the index regions. The probe card is indexed corresponding to the index regions so as to verify all the chips T.
However, since the overhang type needles 31 are used in the conventional probe apparatus, when for example eight chips T are verified at the same time, as shown in FIG. 17C, every (2.times.4) chips are successively verified at the same time as one indexing amount. When all the chips T on the semiconductor wafer are successively verified, as shown in FIG. 2B, the number of chips T to be verified at the right edge of the semiconductor wafer W is small. Thus, in many index regions, the chip area is narrower than the non-chip area. Consequently, the number of times of the indexing operation increases, thereby deteriorating the verification efficiency and lowering the throughput. In addition, since such overhang type probe needles 31 are inclined and long, while the indexing operation is being repeated, the probe needles 31 are repeatedly pressured by the semiconductor wafer or the probe needles are caught in uneven portions on the semiconductor wafer. Thus, the probe needles 31 will be pressured and deformed. Consequently, since the probe needles 31 cannot properly contact the electrode pads P, the probe card should be replaced with a good one, thereby further lowering the throughput.
To solve such a problem, as shown in FIG. 18C, chips T are disposed in such a manner that four chips T are arranged in the vertical direction of one index region and two chips T are arranged in the horizontal direction thereof so as to form the index region in nearly a square shape corresponding to the shape of the semiconductor wafer. Thus, as shown in FIG. 2A, the number of times of the indexing operation can be reduced. However, in this case, since there are four rows of the electrode pads P, two outer rows of the electrode pads P and two inner rows thereof should be contacted to the overhang type probe needles 31 at the same time. To do that, as shown in FIG. 18A, the probe card should be constructed in such a manner that two rows of probe needles are disposed on a securing portion 30 so that the probe needles contact the inner electrode pads (electrode pads on the left side of FIGS. 18A and 18B). In addition, the upper row of the probe needles 31 should be longer than the lower row of the probe needles 31. Thus, the upper row of the probe needles 31 is more easily deformed than the lower row of the probe needles 32. Consequently, when the probe needles 32 are pressured by the semiconductor wafer, as shown in FIG. 18B, the upper row of the probe needles 32 are deformed upward and the probe needles 32 float from the electrode pads P. Thus, the probe card should be replaced, thereby further lowering the throughput.